In the course of developing an electronic circuit design, the designers will invariably need to verify that the design is functionally correct and satisfies physical design constraints. Physical constraints may include timing, space, power consumption and many other factors. Timing analysis provides the designer with information that indicates whether the design, when mapped to particular hardware, satisfies the specified timing constraints such as propagation delays of signals.
Timing analysis may be either static or dynamic. Static timing analysis does not use simulation to determine the expected timing of a logic design, whereas dynamic timing analysis involves simulation. Since dynamic analysis generally requires more hardware resources than does static analysis, it is preferable to subject a design to static timing analysis before proceeding with dynamic analysis and simulation in order to detect and correct any easily identifiable problems.
Both static and dynamic analyses require a mapping of the logic design to specific hardware resources in order to use attributes of those hardware resources for determining timing information. The mapping of the logic design to hardware resources, however, may create challenges for the designer in changing the design to fix any problems. In mapping components of a logic design to hardware resources, a single logic component may be mapped to several hardware resources. Also, for some target hardware devices, for example, field programmable gate arrays (FPGA), multiple logic components may be mapped to a single hardware resource. Thus, it may be difficult for the designer to reconcile the problems reported from the timing analysis with components and connections in the logic design.
The present invention may address one or more of the above issues.